Method to harden shallow trench isolation against total ionizing dose radiation

ABSTRACT

An enhanced shallow trench isolation method for fabricating radiation tolerant integrated circuit devices is disclosed. A layer of pad oxide is first deposited on a semiconductor substrate. A layer of pad nitride is then deposited on the pad oxide layer. A trench is defined within the semiconductor substrate by selectively etching the pad nitride layer, the pad oxide layer, and the semiconductor substrate. Boron ions are then implanted into both the bottom and along the sidewalls of the trench. Subsequently, a trench plug is formed within the trench by depositing an insulating material into the trench and by removing an excess portion of the insulating material A p-well is implanted to a depth just below the depth of the bottom of the trench. This helps to keep the threshold voltage of the IC device below the trench at a high level, and thereby keep post-radiation leakage low. Then, an electrically neutral species is implanted into the wafer.

This disclosure is based upon, and claims priority from, provisionalU.S. Patent Application No. 60/146,895, filed Aug. 2, 1999, the contentsof which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to integrated circuits in general, and inparticular to a method for fabricating integrated circuit devices. Stillmore particularly, the present invention relates to an enhanced shallowtrench isolation method for fabricating radiation-tolerant integratedcircuit devices.

2. Description of the Prior Art

Within a semiconductor integrated circuit (IC) device, device isolationregions can typically be found between two adjacent active components toprevent carriers from traveling between the two adjacent activecomponents. For example, device isolation regions are conventionallyformed between two adjacent field effect transistors (FETs) to reducecharge leakage to and from the two FETs. Often, device isolation regionstake the form of thick field oxide regions extending below the surfaceof a semiconductor substrate. The most common technique for forming athick field oxide region is to use a local oxidation of silicon (LOCOS)processing technique that is well-known to those skilled in the art ofsemiconductor processing. Details related to the LOCOS processingtechniques can be found in VLSI technology, S. M. Sze, McGraw-Hill,1983, which is incorporated by reference herein.

However, bird's beak regions formed in the LOCOS growth of field oxideregions are undesirable because they are typically too thin to provideany impact in terms of device isolation. Bird's beak regionsnevertheless consume substrate surface area, limiting the extent towhich the field oxide region can be shrunk while still providingdesirable levels of device isolation. To provide higher devicedensities, it is therefore desirable to utilize a better deviceisolation structure such as shallow trench isolation (STI). With STItechnology, a sharply defined trench is formed in the semiconductorsubstrate by, for example, anisotropic etching. The trench is filledwith oxide back to the surface of a semiconductor substrate to provide adevice isolation region. Trench isolation regions formed by STI have theadvantages of providing device isolation across their entire lateralextent and of providing a more planar structure.

The present disclosure provides an improved STI method for fabricating ashallow trench that yields a desirable level of radiation tolerance sothat the resulting semiconductor IC device can be used in high-radiationenvironments. Radiation tolerance refers to the ability of asemiconductor IC device to withstand radiation without alteration of itselectrical characteristics. A semiconductor IC device is said to beradiation tolerant if it can continue to function within specificationsafter exposure to a specified amount of radiation.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the present invention, alayer of pad oxide is first deposited on a semiconductor substrate. Alayer of pad nitride is then deposited on the pad oxide layer. A trenchis defined within the semiconductor substrate by selectively etching thepad nitride layer, the pad oxide layer, and the semiconductor substrate.Boron ions are then implanted into both the bottom and along thesidewalls of the trench. Subsequently, a trench plug is formed withinthe trench by depositing an insulating material into the trench and byremoving an excess portion of the insulating material. Since the boronions are implanted at an angle during the above-mentioned ionimplantation step, the semiconductor IC device advantageously exhibitsenhanced radiation-tolerance.

As further steps, a p-well is implanted to a depth just below the depthis of the bottom of the trench. This helps to keep the threshold voltageof the IC device below the trench at a high level; and thereby keeppost-radiation leakage low. Then, an electrically neutral species isimplanted into the wafer. This implant can be a blanket implant over thewhole wafer, or p-channel devices can be shielded from the implant.

Each of these steps can be individually employed to increase radiationhardness over conventional levels. However, the best results areachieved when all of the steps are employed in conjunction with oneanother.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention itself, as well as a preferred mode of use, furtherobjects, and advantages thereof, will best be understood by reference tothe following detailed description of an illustrative embodiment whenread in conjunction with the accompanying drawings, wherein:

FIG. 1 is a pictorial diagram of a semiconductor substrate having alayer of pad oxide and a layer of pad nitride, in accordance with apreferred embodiment of the present invention;

FIG. 2 illustrates the formation of a trench definition mask on thesemiconductor substrate from FIG. 1, in accordance with a preferredembodiment of the present invention;

FIG. 3 illustrates the formation of a trench on the semiconductorsubstrate from FIG. 1, in accordance with a preferred embodiment of thepresent invention;

FIG. 4 is a pictorial illustration of the directional boronimplantations, in accordance with a first aspect of the presentinvention;

FIGS. 5-8 illustrate the formation of a trench plug on the semiconductorsubstrate from FIG. 1, in accordance with a preferred embodiment of thepresent invention;

FIG. 9 illustrates the formation of a P-well, in accordance with asecond aspect of the invention; and

FIG. 10 illustrates the implantation of an electrically neutralmaterial, in accordance with a third aspect of the invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The present invention provides an enhanced shallow trench isolation(STI) method for fabricating radiation tolerant semiconductor integratedcircuit (IC) devices, and a preferred embodiment will be described indetail with reference to the accompanying drawings. The fabricationprocess begins with the division of a semiconductor substrate intoactive regions where active electrical components are to be formed, andisolation regions that electrically separate the active regions.

Referring now to the drawings and in particular to FIG. 1, there isillustrated a pictorial diagram of a semiconductor substrate having alayer of pad oxide and a layer of pad nitride, in accordance with apreferred embodiment of the present invention. As shown, a siliconsubstrate 10 is coated with a layer of thermal oxide that acts as a padoxide layer 11. Pad oxide layer 11 protects the surface of substrate 10from damage in subsequent processing steps. For this purpose, the padoxide layer has a thickness of approximately 100 Å-300 Å. In addition, alayer of silicon nitride that serves as a pad nitride layer 12 is formedon top of pad oxide layer 11. Pad nitride layer 12 may be deposited bychemical vapor deposition (CVD) to a thickness of 1000-3000 Å.

Next, a trench definition mask 14, as depicted in FIG. 2, is formed byexposing and etching a layer of photoresist that was deposited onto padnitride layer 12. Trench definition mask 14 is shaped in the usualmanner so that the surface of pad nitride layer 12 is exposed at aregion x where a trench will be formed. Trench definition mask 14 mayitself be used as the mask for etching layers 12 and 11 as well assubstrate 10 in forming a trench, or trench definition mask 14 may beused to define a mask in pad nitride layer 12 that can then be used forsubsequent etching steps. Most often, a photoresist mask is used todefine the lateral extent of all of the etching steps used in theformation of a trench in substrate 10 because fewer processing a stepsare involved.

A trench 15 is then formed in substrate 10, as illustrated in al FIG. 3,by consecutively etching pad nitride layer 12, pad oxide layer 11, andsubstrate 10. The etching processes used are preferably anisotropic andmay, for example, be performed by reactive ion etching (RIE). Forexample, a gas etchant, such as CF₄ and O₂, is used to etch pad nitridelayer 12 and pad oxide layer 11. Substrate 10 is etched using RIE and amixture of gases including Cl₂, O₂, HBr, and He. The bottom portion oftrench 15 can be etched using SF₆ so that the transition between thebottom and sidewalls of trench 15 is rounded. An appropriate trenchdepth for forming a shallow trench isolation is approximately 2000Å-5000 Å deep. Trench definition mask 14 can be removed at this point.If desired, a thin thermal oxide layer (i.e., sidewall oxide) may begrown on the sidewalls and bottom of trench 15 to remove any defectscreated by the etching processes. If such a thin thermal oxide layer isformed, the thin thermal oxide layer may either be left in place tobecome part of a trench plug (such as trench plug 17 shown in FIG. 6) orbe removed.

With reference now to FIG. 4, there is illustrated a pictorialillustration of directional boron ion implantations, in accordance withone aspect of the present invention. As indicated by arrows 31, boronions are first introduced at an angle in a range of about 0°-7° from avertical axis. Subsequently, a second implantation 32 at a higher angle,in the range of 30°-45°, is carried out. The boron ion implantationsteps preferably have the following parameters: an energy in arelatively low range of about 20 KeV or less, and a concentration ofboron ions in a range between approximately 10¹⁰ atoms/cm² and 10¹³atoms/cm². If there is a sidewall oxide deposited within trench 15, theenergy of the boron ion implantation should be high enough for the boronions to penetrate through the sidewall oxide and stop in substrate 10.Also shown in FIG. 4 is the area of boron ion implantation withinsubstrate 10, which is marked by a dotted line 33.

The low-angle implant provides a high pre-radiation threshold voltagebeneath the trench. Hence, even if a substantial amount of positivecharge is trapped in the trench during irradiation, the field thresholdremains high, and no radiation-induced leakage occurs betweenneighboring n-channel transistors. The higher-angle implant providessimilar results to create a high is threshold voltage along the sidewalls of the trench. This helps to keep radiation-induced leakage lowalong the parasitic sidewall path that typically occurs between thesource and drain within an n-channel transistor.

The implantation of the boron ions at an angle into the field isolationarea can be carried out in a number of different ways. For example, anion beam generator can be mounted in a manner such that it can bepivoted relative to the semiconductor substrate, to emit a beam of ionsat any desired angle relative to the substrate. More preferably,however, the substrate is mounted on a pivoted or gimbaled platform, sothat its orientation relative to a fixed ion beam generator can bevaried during the implantation process, to receive the beam of ions atthe desired angle. Further, although two separate implantation stepshave been described for the bottom and side walls of the trench, asingle continuous implantation could be carried out as well. If desired,conventional lithography techniques can be used to protect channel areasfrom the boron implant.

Next, trench 15 is filled with a layer of silicon oxide 16 by, forexample, low pressure chemical vapor deposition (LPCVD) usingtetraethylortho-siloxane (TEOS) as a source gas. Trench 15 is overfilledduring deposition, as shown in FIG. 5, in order to achieve goodplanarization during subsequent CMP process and to account for possibledensification. Densification of the TEOS oxide is preferablyaccomplished at a temperature of approximately 1000° C. for 10-30minutes. After densification, the portion of the TEOS oxide layerextending above pad nitride layer 12 is removed by chemical mechanicalpolishing (CMP) using pad nitride layer 12 as a stop for the polishingprocess. After the CMP process, some oxide is left inside trench 15 toform a trench plug 17, as depicted in FIG. 6. Although not clearly shownin FIG. 6, the surface of trench plug 17 is recessed slightly below thesurface of pad nitride layer 12 after the CMP process because thesilicon oxide in trench plug 17 is softer than the silicon nitride inpad nitride layer 12.

Pad nitride layer 12 is subsequently removed to expose pad oxide layer11, typically leaving a portion of trench plug 17 extending above thesurface of pad oxide layer 11, as illustrated in FIG. 7. A hydrofluoricacid dip is then used to remove pad oxide layer 11, resulting astructure shown in FIG. 8. A greater depth of trench plug 17 than thatof pad oxide layer 11 is removed during this etching process becausetrench plug 17, which is formed of TEOS, is etched more rapidly than padoxide layer 11, which is formed of thermal oxide.

A sacrificial oxide layer 18 is grown on the surface of substrate 10 forprotecting the surface of substrate 10 and for limiting the channelingof ions implanted in subsequent ion implantation steps. A p-type dopant,such as boron or indium, is then implanted to form a P-well 19, asdepicted in FIG. 9. As a second feature of the invention, the energy ofthe implant is determined so that the depth of the well 19 is just belowthe bottom of the trench 15. This arrangement helps to keep thethreshold beneath the trench at a high level, so that post-radiationleakage remains low.

In an embodiment of the invention where the P-well is formed by a boronimplant, the step of implanting the boron can be carried out inconjunction with, or as part of, the low-angle boron implant 31 thatoccurs prior to filling the trench. Also, conventional photolithographyprocesses can be used to cover p-channel devices during this implant.

As a third step in the radiation hardening of the IC device, anelectrically neutral species, such as germanium, is implanted into thewafer. In carrying out this step, a blanket implant can be performedover the entire wafer, as shown in FIG. 10, or photolithographytechniques can be employed to shield p-channel devices from theimplanted ions. Preferably, high dosage levels are used for thisimplant, for example around 10¹³ atoms/cm² or higher. The implant energyis adjusted to correspond to the implant depth of the n-channeltransistors 34, or both n- and p-channels if a blanket implant isutilized. More specifically, the energy of the implant should beregulated to limit the implantation to a depth 35 which ensures that theelectrically neutral species remain in the n⁺ and p⁺ diffusion regions.If the implant extends into the junction between these diffusion regionsand the well, the diode which results from this junction could be leaky.

Sacrificial oxide layer 18 is subsequently removed, once again using ahydrofluoric acid dip. The semiconductor substrate is thereaftersubjected to further processing to complete a fabrication of asemiconductor a IC device. A description of those further processingsteps, which are known to those skilled in the relevant art, is notnecessary to an understanding of the present invention, and thereforenot presented herein.

As has been described, the present invention provides an enhanced STImethod for fabricating radiation-tolerant IC devices. The increase inradiation tolerance is attributable to the implantation of boron ions atan angle during an boron ion implantation step. As a result, a higherp-type concentration can be maintained under the field oxide regions ofthe substrate. Because of the high p-type concentration in thesubstrate, the substrate is able to withstand a relatively high dose ofradiation before any inversion occurs at the surface of the substrate.Further enhancements are provided by implanting the p-well to a depthjust below the bottom of the trench, and by implanting an electricallyneutral species into the wafer. In view of such, IC devices that arefabricated using the present invention exhibit enhancedradiation-tolerance.

While the invention has been particularly shown and described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

1. A method for fabricating radiation-tolerant integrated circuitdevices, said method comprising: depositing a layer of pad oxide on asemiconductor substrate; selectively etching said pad oxide layer andsaid semiconductor substrate to define a trench within saidsemiconductor substrate; and implanting boron ions at an angle withrespect to normal in said trench.
 2. The method according to claim 1,wherein said boron ions are implanted beneath the bottom of the trenchend along the side walls of the trench.
 3. The method according to claim1, wherein said boron ion implantation is performed with an energy nogreater than about 20 KeV.
 4. The method according to claim 1, whereinsaid boron ion implantation is performed with a dose of boron ions in arange between approximately 10¹⁰ atoms/cm² and 10¹³ atoms/cm².
 5. Themethod according to claim 1, further including the step of implanting ap-type material to form a P-well having a depth greater than the depthof said trench.
 6. The method according to claim 5, further includingthe step of implanting an electrically neutral material into saidsubstrate.
 7. The, method according to claim 6, wherein saidelectrically neutral material is implanted to a depth which is nogreater than the depth of a diffusion region in said P-well.
 8. Asemiconductor integrated circuit device, comprising: a semiconductorsubstrate having a layer of pad oxide and a patterned pad nitride; and ashallow trench formed within said semiconductor substrate, whichincludes a implantation region formed by implanting boron ions below thebottom and along the side walls of said shallow trench.
 9. Thesemiconductor integrated circuit device according to claim 8, furtherincluding a P-well having a depth which is greater than the depth ofsaid trench.
 10. The semiconductor integrated circuit device accordingto claim 9, further including an implantation region of electricallyneutral material.
 11. The semiconductor integrated circuit deviceaccording to claim 10, wherein said P-well has diffusion regions withinit, and said implantation region of electrically neutral materialextends to a depth less than the depth of said diffusion regions. 12.The semiconductor integrated circuit device according to claim 8,wherein said boron ions have a concentration between approximately 10¹⁰atoms/cm² and 10¹³ atoms/cm².